Commercial interest in DSSS communication systems has recently risen due to their potential in providing services to more users than is offered by other multiple access systems. In a cell site station of a DS/CDMA system, a data symbol is spread by multiplying it with higher frequency orthogonal pseudo-random number sequences assigned to the cell site.
The primary function of pseudo-random noise (PN) code synchronization in spread spectrum communication systems, such as the Code Division Multiple Access Direct Sequence Spread Spectrum (CDMA-DSSS) system, is to despread the received PN code for demodulation of the received signal. The received signal in essence consists of two digital signals or bit streams that are combined to create a modulated third signal prior to transmission. The first digital signal is an information signal, such as from the output of a digitized voice circuit, which may have a bit rate, for example, of 10 kb/s. The second signal is generated by a random-sequence or pseudonoise (PN) generator and constitutes a stream of essentially random bits having a bit rate that is several orders of magnitude greater than that of the digitized voice signal. The combination or modulated third signal that is actually transmitted has the same bit rate as the faster second signal while containing the slower voice signal.
At the receiver, after carrier frequency demodulation, despreading is accomplished by generating a local replica of the PN code with a random-sequence generator in the receiver and then synchronizing the local PN signal to the one that has been superimposed on the incoming received signal. By removing the random sequence from the received signal and integrating it over a symbol period, a despread signal is obtained which ideally represents the recovered original 10 kb/s voice signal.
The process of signal synchronization is usually accomplished in two steps. The first step, called acquisition, consists of bringing the two codes or spreading signals into coarse time alignment within one code chip interval. The second step, called tracking, takes over and continuously maintains the best possible waveform alignment by means of a feedback loop. The focus of the present invention is on the acquisition aspect of signal synchronization.
Because of the importance of synchronization (or acquisition), many schemes have been proposed which utilized various types of detectors and decision strategies in different application areas. A common feature of most synchronization schemes is that the received signal and the locally generated signal are first correlated to produce a measure of similarity. The correlation result is compared to a threshold to decide if the two signals are in synchronism. If synchronization is detected, the tracking loop takes over. If there is no synchronization, the acquisition process continues. Typically, the phase of the locally generated PN code is changed and another correlation is attempted until the correlation result exceeds a certain threshold, signifying synchronization or acquisition.
As explained above, a DSSS communication system which restores phase is called a synchronization system. In such system, two methods of acquisition, serial or parallel, are generally used. The parallel acquisition method may have performance better than the serial acquisition method, but high performance hardware is needed due to the more complex functional requirements. For this and other reasons, serial acquisition techniques or systems are more widely used.
FIG. 1 is a block diagram showing a conventional synchronization spread spectrum system capable of implementing serial acquisition. In the system, a PN despreading operation is accomplished by multiplying a PN code signal with a form of an input Signal received from the receiver antenna. The PN code signal is output from PN code generator 12. The input Signal is converted to a digital signal by an analog-to-digital converter 10, which is sampled by clock signal CLK1 which corresponds to a chip clock signal. The digital data output from the analog-to-digital converter 10 is time-ordered with latch 11 and clocked by CLK 2. The output of multiplier 13 is accumulated by accumulator 14 the values is correlated and compared with a threshold value in comparator 17. If the correlation or accumulation value is greater than the threshold value, acquisition is accomplished. If the correlation value is less than the threshold value, the system holds the PN code signal generated from the PN code generator 12, and the synchronization and correlation process repeats for other phases of the input Signal until synchronization with the proper phase is achieved.
It can be seen that with the conventional serial acquisition method described above correlation may not be accomplished until after several attempts with different phases of the input signal. A need exists for a serial acquisition process corresponding to a chip clock cycle which is more time efficient.